Today's very large scale integrated circuits typically use CMOS technology. CMOS technology is advantageous in very large scale integrated circuit applications because of its relatively small power dissipation. CMOS devices include combinations of n-channel MOS (NMOS) and p-channel MOS (PMOS) transistors on adjacent regions of a semiconductor chip. FIG. 1 is a simplified illustration of a cross-section of a semiconductor chip 100. Regions of n-type material and p-type material are shown for p-channel device 102 and n-channel device 104. Regions of p-type or n-type material are also known as diffusion areas. Diffusion refers to the net motion of charge carriers from regions of high carrier concentration to regions of low carrier concentration. Diffusion represents the charge transport process in semiconductors.
As semiconductor chips become ever larger, incorporating ever more devices, it becomes increasingly important to minimize semiconductor area used by a given number of devices. Conservation of semiconductor area is a primary goal in semiconductor chip development because even a small added semiconductor area potentially translates into millions of dollars. Another goal of semiconductor development is to improve device performance. Device performance, simply stated, is the ability of the circuit to operate correctly with as great a speed as possible. The goal of saving semiconductor area and the goal of increasing device performance are usually interrelated. For instance, if devices are placed on a semiconductor chip closer together, the length charge must travel is reduced and greater speed is realized.
Various design factors complicate the task of designing a circuit for a semiconductor chip so as to minimize area usage. For example, transistor sizes vary in practical circuit designs, resulting in non-uniform transistor heights, which can lead to wasted semiconductor area.
Several techniques have been developed to address the problem of achieving optimal layout, where optimal layout refers to an arrangement of devices on a semiconductor chip so as to minimize area and maximize performance. One technique conserves area by placing transistors so as to share diffusion area. FIG. 2 illustrates this technique. Transistor layout 203 is a representation of a layout of a transistor whose schematic representation is 202. Similarly, transistor layout 205 represents a possible layout of a transistor represented by schematic 204. Because of the orientation of a drain diffusion area to the left of layout 205 and to the right of layout 203, the two transistors can be placed such that they share the drain diffusion area.
Another technique for conserving semiconductor area is known as transistor folding. Transistor folding is a process of converting a transistor into smaller, multiple transistors called folds, or legs, which are connected in parallel and must be placed together on a semiconductor chip. Transistors are folded in order to meet predetermined maximum height requirements. FIG. 3 shows a transistor before and after folding. Schematic 302 shows one transistor before folding. Schematic 306 is equivalent to schematic 302. Schematic 306 represents the transistor of schematic 302 after folding into two legs or folds. Layout 304 represents a layout of schematic 302. Layout 308 is one possible layout of schematic 306. Layout 310 is an alternate possible layout of schematic 306. Layout 308 is referred to as an unflipped orientation, and layout 310 is referred to as a flipped orientation.
The orientation of transistors after folding can have an effect on area usage. For example, note that two layouts 308 or two layouts 310 can be abutted so that a diffusion area is shared. However, a layout 308 and layout 310 cannot be abutted because the source and drain diffusion areas are not electrically equivalent.
Transistors which are abutted in a layout form transistor chains. It is desirable to produce a layout with a maximum number of transistors chained so as to minimize diffusion gaps.
Thus, a variety of available design techniques such as chaining of transistors, folding of transistors and flipping of folded transistors are available to the layout designer. This variety makes the transistor circuit layout process extremely complex. For this reason, design of transistor circuit layouts is a major contribution to design cycle time and cost.
Software tools currently exist which automatically generate layouts of a given circuit based upon cells, where a cell is an arrangement of transistors without multiple levels of hierarchy. Such tools are known as cell synthesis tools. Cell synthesis tools typically take a circuit description as input in the form of a net list or a schematic and output a graphical layout showing arrangement of transistors as an arrangement of diffusion areas on a semiconductor chip. Cell synthesis tools make layout design faster, but benefits of prior synthesis tools are limited by their inability to fully consider design constraints or to take full advantage of techniques which save semiconductor area and increase circuit performance.
One limitation of some prior art cell synthesis tools is that they make several impractical simplifying assumptions about the circuit. For example, they assume an equal number of p-type devices and n-type devices, uniform transistor size, and no transistor folding. Some prior art cell synthesis tools can perform transistor folding, but only perform simple transistor folding in a way that significantly decreases the effectiveness of the folding technique in producing improved layouts. Typically, prior art cell synthesis tools receive a circuit description and then map the circuit to a semiconductor chip. Mapping, also known as placing, is the process of specifying transistor locations on a physical device. After placement, simple folding is then performed without consideration of all possible orientations of transistors. Significantly, prior cell synthesis tools also fail to consider all possible combinations of transistors to produce chains. This results in a sub-optimal circuits with respect to area and performance. For example, because different orientations of transistors are not considered (flipped and unflipped), unnecessary diffusion gaps usually exist as explained previously with respect to FIG. 3.
For these reasons, graphical layouts produced using prior art cell synthesis tools usually require extensive manual rearrangement to improve performance and decrease area. This manual rearrangement adds to the overall cost of development and production. In addition, with manual optimization, there is no guarantee that device arrangements have been exhaustively sampled to produce an optimum achievable layout that meets all physical design rules.
As will be shown, the present invention provides an improved method and apparatus that more advantageously uses optimization techniques to produce a cell layout of minimum area that meets design constraints and physical design rules.